TY - JOUR
T1 - Satisfiability modulo graph theory for task mapping and scheduling on multiprocessor systems
AU - Liu, Weichen
AU - Gu, Zonghua
AU - Xu, Jiang
AU - Wu, Xiaowen
AU - Ye, Yaoyao
PY - 2011
Y1 - 2011
N2 - Task graph scheduling on multiprocessor systems is a representative multiprocessor scheduling problem. A solution to this problem consists of the mapping of tasks to processors and the scheduling of tasks on each processor. Optimal solution can be obtained by exploring the entire design space of all possible mapping and scheduling choices. Since the problem is NP-hard, scalability becomes the main concern in solving the problem optimally. In this paper, a SAT-based optimization framework is proposed to address this problem, in which SAT solver is enhanced by integrating with a scheduling analysis tool in a branch and bound manner to prune the solution space efficiently. Performance evaluation results show that our technique has average performance improvement in more than an order of magnitude compared to state-of-the-art techniques. We further build a cycle-accurate network-on-chip simulator based on SystemC to verify the effectiveness of the proposed technique on realistic multiprocessor systems.
AB - Task graph scheduling on multiprocessor systems is a representative multiprocessor scheduling problem. A solution to this problem consists of the mapping of tasks to processors and the scheduling of tasks on each processor. Optimal solution can be obtained by exploring the entire design space of all possible mapping and scheduling choices. Since the problem is NP-hard, scalability becomes the main concern in solving the problem optimally. In this paper, a SAT-based optimization framework is proposed to address this problem, in which SAT solver is enhanced by integrating with a scheduling analysis tool in a branch and bound manner to prune the solution space efficiently. Performance evaluation results show that our technique has average performance improvement in more than an order of magnitude compared to state-of-the-art techniques. We further build a cycle-accurate network-on-chip simulator based on SystemC to verify the effectiveness of the proposed technique on realistic multiprocessor systems.
KW - Multiprocessor
KW - design space exploration
KW - satisfiability
KW - scheduling
UR - https://www.webofscience.com/wos/woscc/full-record/WOS:000292047500014
UR - https://openalex.org/W2142743910
UR - https://www.scopus.com/pages/publications/79959726381
U2 - 10.1109/TPDS.2010.204
DO - 10.1109/TPDS.2010.204
M3 - Journal Article
SN - 1045-9219
VL - 22
SP - 1382
EP - 1389
JO - IEEE Transactions on Parallel and Distributed Systems
JF - IEEE Transactions on Parallel and Distributed Systems
IS - 8
M1 - 5639008
ER -