Abstract
The optimization of shift‐and‐add network for constant multiplications is found to have great potential for reducing the area, delay, and power consumption of implementation of multiplications in several computation‐intensive applications not only in dedicated hardware but also in programmable computing systems. To simplify the shift‐and‐add network in single constant multiplication (SCM) circuits, this chapter discusses three design approaches, including direct simplification from a given number representation, simplification by redundant signed digit (SD) representation, and simplification by adder graph. Examples of the multiple constant multiplication (MCM) methods are constant matrix multiplication, discrete cosine transform (DCT) or fast Fourier transform (FFT), and polyphase finite impulse response (FIR) filters and filter banks. The given constant multiplication methods can be used for matrix multiplications and inner‐product; and can be applied easily to image/video processing and graphics applications. The chapter further discusses some of the shortcomings in the current research on constant multiplications, and possible scopes of improvement.
| Original language | English |
|---|---|
| Title of host publication | Arithmetic Circuits for DSP Applications |
| Publisher | The Institute of Electrical and Electronics Engineers, Inc. |
| Pages | 33-76 |
| ISBN (Print) | 9781119206774 |
| DOIs | |
| Publication status | Published - Aug 2017 |
| Externally published | Yes |