TY - JOUR
T1 - SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect
AU - Sang, Ling
AU - Jin, Rui
AU - Cui, Jiawei
AU - Niu, Xiping
AU - Li, Zheyang
AU - Yang, Junjie
AU - Nuo, Muqin
AU - Zhang, Meng
AU - Wang, Maojun
AU - Wei, Jin
N1 - Publisher Copyright:
© 2024 by the authors.
PY - 2024/5
Y1 - 2024/5
N2 - A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.
AB - A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.
KW - SiC MOSFET
KW - dynamic threshold voltage
KW - fin-channel
KW - gate shielding effect
UR - https://www.webofscience.com/wos/woscc/full-record/WOS:001219809900001
UR - https://www.scopus.com/pages/publications/85192710199
U2 - 10.3390/electronics13091701
DO - 10.3390/electronics13091701
M3 - Journal Article
SN - 2079-9292
VL - 13
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 9
M1 - 1701
ER -