SJ-FINFET: A new low voltage lateral superjunction MOSFET

Y. Onishi*, H. Wang, H. P.E. Xu, W. T. Ng, R. Wu, J. K.O. Sin

*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/ReportConference Paper published in a bookpeer-review

25 Citations (Scopus)

Abstract

This paper proposes a new SOI lateral superjunction (SJ) power transistor structure, SJ-FINFET, to address the requirement for low voltage lateral MOSFETs with low specific on-resistance (Ron,sp). The SJ-FINFET consists of a 3D trench gate and a SJ drift region (the fin) to reduce both the channel resistance and the drift region resistance. The SJ-FINFET with n/p-drift region pillar thickness (SOI layer thickness, Tepi) of 4μm was simulated and found to have a Ron,sp of 0.18mΩ·cm2. This is 21% lower than the well-known silicon limit at a breakdown voltage (BVdss) of 68V.

Original languageEnglish
Title of host publicationISPSD '08, Proceedings of the 20th International Symposium on Power Semiconductor Devices and IC's
Pages111-114
Number of pages4
DOIs
Publication statusPublished - 2008
EventISPSD '08, 20th International Symposium on Power Semiconductor Devices and IC's - Orlando, FL, United States
Duration: 18 May 200822 May 2008

Publication series

NameProceedings of the International Symposium on Power Semiconductor Devices and ICs
ISSN (Print)1063-6854

Conference

ConferenceISPSD '08, 20th International Symposium on Power Semiconductor Devices and IC's
Country/TerritoryUnited States
CityOrlando, FL
Period18/05/0822/05/08

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