Speeding up power estimation by topological analysis

David Ihsin Cheng; Malgorzata Marek-Sadowska; Kwang Ting Cheng

Speeding up power estimation by topological analysis

David Ihsin Cheng^*, Malgorzata Marek-Sadowska, Kwang Ting Cheng

^*Corresponding author for this work

Research output: Contribution to journal › Conference article published in journal › peer-review

4 Citations (Scopus)

Abstract

We present an efficient technique to speedup the power estimation process for combinational circuits. Our approach is based on a topological analysis of the underlying circuit using the concept of supergates. We also present an optimal algorithm for calculating the supergate structures. In addition to speeding up, we also point out that certain nodes in a given circuit are more crucial than other nodes to be estimated accurately. Experimental results are very encouraging.

Original language	English
Pages (from-to)	623-626
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1995
Externally published	Yes
Event	Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 1 May 1995 → 4 May 1995

Cite this

@article{44842212327a4b52a76e3c9f4b913661,

title = "Speeding up power estimation by topological analysis",

abstract = "We present an efficient technique to speedup the power estimation process for combinational circuits. Our approach is based on a topological analysis of the underlying circuit using the concept of supergates. We also present an optimal algorithm for calculating the supergate structures. In addition to speeding up, we also point out that certain nodes in a given circuit are more crucial than other nodes to be estimated accurately. Experimental results are very encouraging.",

author = "Cheng, \{David Ihsin\} and Malgorzata Marek-Sadowska and Cheng, \{Kwang Ting\}",

year = "1995",

language = "English",

pages = "623--626",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference ; Conference date: 01-05-1995 Through 04-05-1995",

}

TY - JOUR

T1 - Speeding up power estimation by topological analysis

AU - Cheng, David Ihsin

AU - Marek-Sadowska, Malgorzata

AU - Cheng, Kwang Ting

PY - 1995

Y1 - 1995

N2 - We present an efficient technique to speedup the power estimation process for combinational circuits. Our approach is based on a topological analysis of the underlying circuit using the concept of supergates. We also present an optimal algorithm for calculating the supergate structures. In addition to speeding up, we also point out that certain nodes in a given circuit are more crucial than other nodes to be estimated accurately. Experimental results are very encouraging.

AB - We present an efficient technique to speedup the power estimation process for combinational circuits. Our approach is based on a topological analysis of the underlying circuit using the concept of supergates. We also present an optimal algorithm for calculating the supergate structures. In addition to speeding up, we also point out that certain nodes in a given circuit are more crucial than other nodes to be estimated accurately. Experimental results are very encouraging.

UR - https://www.scopus.com/pages/publications/0029216459

M3 - Conference article published in journal

AN - SCOPUS:0029216459

SN - 0886-5930

SP - 623

EP - 626

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference

Y2 - 1 May 1995 through 4 May 1995

ER -

Speeding up power estimation by topological analysis

Abstract

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