Abstract
A robust SRAM cell that can tolerate metallic carbon nanotubes is presented in this paper. A statistical yield model of carbon nanotube transistors and memory circuits is developed considering spatial correlations. The yield of the proposed process-imperfections-aware SRAM array is increased by more than twenty-one thousand times as compared to an alternative design that assumes perfect carbon nanotubes in a 16nm technology.
| Original language | English |
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| Title of host publication | ICEIC 2019 - International Conference on Electronics, Information, and Communication |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9788995004449 |
| DOIs | |
| Publication status | Published - 3 May 2019 |
| Event | 18th International Conference on Electronics, Information, and Communication, ICEIC 2019 - Auckland, New Zealand Duration: 22 Jan 2019 → 25 Jan 2019 |
Publication series
| Name | ICEIC 2019 - International Conference on Electronics, Information, and Communication |
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Conference
| Conference | 18th International Conference on Electronics, Information, and Communication, ICEIC 2019 |
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| Country/Territory | New Zealand |
| City | Auckland |
| Period | 22/01/19 → 25/01/19 |
Bibliographical note
Publisher Copyright:© 2019 Institute of Electronics and Information Engineers (IEIE).
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