System-on-chip design for a statistical decoder

Liang Hao Wang; Zheng Zhu; Kai Luo; Bingbo Li; Ming Zhang

doi:10.1109/ICASIC.2007.4415793

System-on-chip design for a statistical decoder

Liang Hao Wang^*, Zheng Zhu, Kai Luo, Bingbo Li, Ming Zhang

^*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

4 Citations (Scopus)

Abstract

In this paper, we propose a system-on-chip software hardware co-design for a statistical decoder. We use the Context-based Adaptive Binary Arithmetic Decoder (CABAC decoder) used in the High profile of the H.264/AVC video coding standard as a design example. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. It is capable of decoding one bin per clock cycle at high clock frequencies while maintaining a slim hardware footprint. Compared to existing statistical decoders, this design is aimed for a fast and compact IP core, well verified with standard video test sequence, and ideal for a SoC implementation.

Original language	English
Title of host publication	ASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages	966-969
Number of pages	4
DOIs	https://doi.org/10.1109/ICASIC.2007.4415793
Publication status	Published - 2007
Externally published	Yes
Event	2007 7th International Conference on ASIC, ASICON 2007 - Guilin, China Duration: 26 Oct 2007 → 29 Oct 2007

Publication series

Name	ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Conference

Conference	2007 7th International Conference on ASIC, ASICON 2007
Country/Territory	China
City	Guilin
Period	26/10/07 → 29/10/07

Access to Document

10.1109/ICASIC.2007.4415793

Cite this

@inproceedings{88bb19961ebd4b8b97cd7f8557dceb34,

title = "System-on-chip design for a statistical decoder",

abstract = "In this paper, we propose a system-on-chip software hardware co-design for a statistical decoder. We use the Context-based Adaptive Binary Arithmetic Decoder (CABAC decoder) used in the High profile of the H.264/AVC video coding standard as a design example. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. It is capable of decoding one bin per clock cycle at high clock frequencies while maintaining a slim hardware footprint. Compared to existing statistical decoders, this design is aimed for a fast and compact IP core, well verified with standard video test sequence, and ideal for a SoC implementation.",

author = "Wang, \{Liang Hao\} and Zheng Zhu and Kai Luo and Bingbo Li and Ming Zhang",

year = "2007",

doi = "10.1109/ICASIC.2007.4415793",

language = "English",

isbn = "1424411327",

series = "ASICON 2007 - 2007 7th International Conference on ASIC Proceeding",

pages = "966--969",

booktitle = "ASICON 2007 - 2007 7th International Conference on ASIC Proceeding",

note = "2007 7th International Conference on ASIC, ASICON 2007 ; Conference date: 26-10-2007 Through 29-10-2007",

}

Wang, LH, Zhu, Z, Luo, K, Li, B & Zhang, M 2007, System-on-chip design for a statistical decoder. in ASICON 2007 - 2007 7th International Conference on ASIC Proceeding., 4415793, ASICON 2007 - 2007 7th International Conference on ASIC Proceeding, pp. 966-969, 2007 7th International Conference on ASIC, ASICON 2007, Guilin, China, 26/10/07. https://doi.org/10.1109/ICASIC.2007.4415793

System-on-chip design for a statistical decoder. / Wang, Liang Hao; Zhu, Zheng; Luo, Kai et al.
ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. p. 966-969 4415793 (ASICON 2007 - 2007 7th International Conference on ASIC Proceeding).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - System-on-chip design for a statistical decoder

AU - Wang, Liang Hao

AU - Zhu, Zheng

AU - Luo, Kai

AU - Li, Bingbo

AU - Zhang, Ming

PY - 2007

Y1 - 2007

N2 - In this paper, we propose a system-on-chip software hardware co-design for a statistical decoder. We use the Context-based Adaptive Binary Arithmetic Decoder (CABAC decoder) used in the High profile of the H.264/AVC video coding standard as a design example. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. It is capable of decoding one bin per clock cycle at high clock frequencies while maintaining a slim hardware footprint. Compared to existing statistical decoders, this design is aimed for a fast and compact IP core, well verified with standard video test sequence, and ideal for a SoC implementation.

AB - In this paper, we propose a system-on-chip software hardware co-design for a statistical decoder. We use the Context-based Adaptive Binary Arithmetic Decoder (CABAC decoder) used in the High profile of the H.264/AVC video coding standard as a design example. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. It is capable of decoding one bin per clock cycle at high clock frequencies while maintaining a slim hardware footprint. Compared to existing statistical decoders, this design is aimed for a fast and compact IP core, well verified with standard video test sequence, and ideal for a SoC implementation.

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DO - 10.1109/ICASIC.2007.4415793

M3 - Conference Paper published in a book

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SN - 9781424411320

T3 - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

SP - 966

EP - 969

BT - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

T2 - 2007 7th International Conference on ASIC, ASICON 2007

Y2 - 26 October 2007 through 29 October 2007

ER -

System-on-chip design for a statistical decoder

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