Test consideration for nanometer scale CMOS circuits

K. Roy; T. M. Mak; Kwang Ting Cheng

doi:10.1109/VTEST.2003.1197668

Test consideration for nanometer scale CMOS circuits

K. Roy, T. M. Mak, Kwang Ting Cheng

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

3 Citations (Scopus)

Abstract

The ITRS (international technology roadmap for semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing demands for performance. Such scaling will result in an exponential increase in leakage current and large variability in threshold voltage both within and across dies. Device counts will increase from about 0.2 B/chip today to approximately 10 B/chip in a decade. This 50× increase in device count will increase not only the active power dissipation, but also the standby or the quiescent power. Hence, designers are required to use innovative aggressive power management strategies to meet the power constraints. The exponential increase in leakage, the device parameter variations, and aggressive power management techniques are expected to severely impact the way integrated circuits are tested today. This paper explores test considerations for the scaled CMOS circuits in the nanometer regime.

Original language	English
Title of host publication	Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003
Publisher	IEEE Computer Society
Pages	313-315
Number of pages	3
ISBN (Electronic)	0769519245
DOIs	https://doi.org/10.1109/VTEST.2003.1197668
Publication status	Published - 2003
Externally published	Yes
Event	21st IEEE VLSI Test Symposium, VTS 2003 - Napa Valley, United States Duration: 27 Apr 2003 → 1 May 2003

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	2003-January

Conference

Conference	21st IEEE VLSI Test Symposium, VTS 2003
Country/Territory	United States
City	Napa Valley
Period	27/04/03 → 1/05/03

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

Keywords

CMOS technology
Circuit testing
Energy consumption
Energy management
Frequency
Integrated circuit testing
Leakage current
Temperature sensors
Threshold voltage
Tunneling

Access to Document

10.1109/VTEST.2003.1197668

Cite this

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title = "Test consideration for nanometer scale CMOS circuits",

abstract = "The ITRS (international technology roadmap for semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing demands for performance. Such scaling will result in an exponential increase in leakage current and large variability in threshold voltage both within and across dies. Device counts will increase from about 0.2 B/chip today to approximately 10 B/chip in a decade. This 50× increase in device count will increase not only the active power dissipation, but also the standby or the quiescent power. Hence, designers are required to use innovative aggressive power management strategies to meet the power constraints. The exponential increase in leakage, the device parameter variations, and aggressive power management techniques are expected to severely impact the way integrated circuits are tested today. This paper explores test considerations for the scaled CMOS circuits in the nanometer regime.",

keywords = "CMOS technology, Circuit testing, Energy consumption, Energy management, Frequency, Integrated circuit testing, Leakage current, Temperature sensors, Threshold voltage, Tunneling",

author = "K. Roy and Mak, \{T. M.\} and Cheng, \{Kwang Ting\}",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 21st IEEE VLSI Test Symposium, VTS 2003 ; Conference date: 27-04-2003 Through 01-05-2003",

year = "2003",

doi = "10.1109/VTEST.2003.1197668",

language = "English",

series = "Proceedings of the IEEE VLSI Test Symposium",

publisher = "IEEE Computer Society",

pages = "313--315",

booktitle = "Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003",

}

Roy, K, Mak, TM & Cheng, KT 2003, Test consideration for nanometer scale CMOS circuits. in Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003., 1197668, Proceedings of the IEEE VLSI Test Symposium, vol. 2003-January, IEEE Computer Society, pp. 313-315, 21st IEEE VLSI Test Symposium, VTS 2003, Napa Valley, United States, 27/04/03. https://doi.org/10.1109/VTEST.2003.1197668

Test consideration for nanometer scale CMOS circuits. / Roy, K.; Mak, T. M.; Cheng, Kwang Ting.
Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003. IEEE Computer Society, 2003. p. 313-315 1197668 (Proceedings of the IEEE VLSI Test Symposium; Vol. 2003-January).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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T1 - Test consideration for nanometer scale CMOS circuits

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AU - Mak, T. M.

AU - Cheng, Kwang Ting

PY - 2003

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N2 - The ITRS (international technology roadmap for semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing demands for performance. Such scaling will result in an exponential increase in leakage current and large variability in threshold voltage both within and across dies. Device counts will increase from about 0.2 B/chip today to approximately 10 B/chip in a decade. This 50× increase in device count will increase not only the active power dissipation, but also the standby or the quiescent power. Hence, designers are required to use innovative aggressive power management strategies to meet the power constraints. The exponential increase in leakage, the device parameter variations, and aggressive power management techniques are expected to severely impact the way integrated circuits are tested today. This paper explores test considerations for the scaled CMOS circuits in the nanometer regime.

AB - The ITRS (international technology roadmap for semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing demands for performance. Such scaling will result in an exponential increase in leakage current and large variability in threshold voltage both within and across dies. Device counts will increase from about 0.2 B/chip today to approximately 10 B/chip in a decade. This 50× increase in device count will increase not only the active power dissipation, but also the standby or the quiescent power. Hence, designers are required to use innovative aggressive power management strategies to meet the power constraints. The exponential increase in leakage, the device parameter variations, and aggressive power management techniques are expected to severely impact the way integrated circuits are tested today. This paper explores test considerations for the scaled CMOS circuits in the nanometer regime.

KW - CMOS technology

KW - Circuit testing

KW - Energy consumption

KW - Energy management

KW - Frequency

KW - Integrated circuit testing

KW - Leakage current

KW - Temperature sensors

KW - Threshold voltage

KW - Tunneling

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BT - Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003

PB - IEEE Computer Society

T2 - 21st IEEE VLSI Test Symposium, VTS 2003

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ER -

Test consideration for nanometer scale CMOS circuits

Abstract

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Bibliographical note

Keywords

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