Test consideration for nanometer-scale CMOS circuits

Roy Kaushik; T. M. Mak; Kwang Tim Cheng

doi:10.1109/MDT.2006.52

Test consideration for nanometer-scale CMOS circuits

Roy Kaushik, T. M. Mak, Kwang Tim Cheng

Research output: Contribution to journal › Journal Article › peer-review

15 Citations (Scopus)

Abstract

Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. This article describes possible solutions to many of these challenges, including statistical timing and delay test, I_DDQ test under exponentially increasing leakage, and power or thermal management architectures.

Original language	English
Pages (from-to)	128-136
Number of pages	9
Journal	IEEE Design and Test of Computers
Volume	23
Issue number	2
DOIs	https://doi.org/10.1109/MDT.2006.52
Publication status	Published - Mar 2006
Externally published	Yes

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10.1109/MDT.2006.52

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abstract = "Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. This article describes possible solutions to many of these challenges, including statistical timing and delay test, IDDQ test under exponentially increasing leakage, and power or thermal management architectures.",

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Test consideration for nanometer-scale CMOS circuits

Abstract

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