Test generation for delay faults in non-scan and partial scan sequential circuits

We address the problem of generating tests for delay faults in non-scan and partial scan synchronous sequential circuits. A recently proposed transition fault model for sequential circuits is considered. In this fault model, a transition fault is characterized by the fault site, the fault type and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. It was observed that neither a comprehensive functional verification sequence nor a sequence with a high stuck-at fault coverage gives a high transition fault coverage for sequential circuits. Deterministic test generation for delay faults is required to raise the coverage to a reasonable level. In this paper, we present a test generation algorithm for this fault model. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck-at fault test generation algorithm with some modifications. The new test generator DATEST (Delay fault Automatic TEST generator for sequential circuits) has been integrated with our sequential circuit delay fault simulator, TFSIM. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. For partial scan circuits, we first describe a test application scheme for detecting transition faults. Modifications on test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle-breaking technique.