The impact of device scaling and power supply change on CMOS gate performance

Kai Chen; H. Clement Wann; Ping K. Ko; Chenming Hu

doi:10.1109/55.491829

The impact of device scaling and power supply change on CMOS gate performance

Kai Chen^*, H. Clement Wann, Ping K. Ko, Chenming Hu

^*Corresponding author for this work

Research output: Contribution to journal › Journal Article › peer-review

47 Citations (Scopus)

Abstract

Based a new empirical mobility model that's solely dependent on V_gs, V_t, and T_or and a corresponding saturation drain current (I_dsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the T_ox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V_dd (for low power applications) if V_t can be lowered.

Original language	English
Pages (from-to)	202-204
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	17
Issue number	5
DOIs	https://doi.org/10.1109/55.491829
Publication status	Published - May 1996
Externally published	Yes

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title = "The impact of device scaling and power supply change on CMOS gate performance",

abstract = "Based a new empirical mobility model that's solely dependent on Vgs, Vt, and Tor and a corresponding saturation drain current (Idsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the Tox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low Vdd (for low power applications) if Vt can be lowered.",

author = "Kai Chen and Wann, \{H. Clement\} and Ko, \{Ping K.\} and Chenming Hu",

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AU - Wann, H. Clement

AU - Ko, Ping K.

AU - Hu, Chenming

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N2 - Based a new empirical mobility model that's solely dependent on Vgs, Vt, and Tor and a corresponding saturation drain current (Idsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the Tox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low Vdd (for low power applications) if Vt can be lowered.

AB - Based a new empirical mobility model that's solely dependent on Vgs, Vt, and Tor and a corresponding saturation drain current (Idsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the Tox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low Vdd (for low power applications) if Vt can be lowered.

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DO - 10.1109/55.491829

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JO - IEEE Electron Device Letters

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The impact of device scaling and power supply change on CMOS gate performance

Abstract

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