Abstract
Bottom-gate thin-film transistors (TFTs) are currently fabricated using either a three-mask back-channel-etched (BCE) or, with an additional mask for the definition of an etch-stop (ES) layer, a four-mask technology. The former offers a lower cost of manufacturing and a higher resolution, while the latter provides better device characteristics in terms of both performance and reliability. Presently reported is a three-mask process for realizing an elevated-metal metal-oxide TFT employing self-aligned patterning of the active island, also inherently incorporating an ES layer. This technology offers a TFT that combines the same protection of the channel, and hence, the good characteristics of an ES TFT, with the lower cost, reduced parasitic overlap capacitance, and smaller device-footprint of a BCE TFT.
| Original language | English |
|---|---|
| Article number | 81146 |
| Pages (from-to) | 35-38 |
| Number of pages | 4 |
| Journal | IEEE Electron Device Letters |
| Volume | 39 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 1 Jul 2018 |
Bibliographical note
Publisher Copyright:© 1980-01 IEEE.
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SDG 9 Industry, Innovation, and Infrastructure
Keywords
- Elevated-metal metal oxide (EMMO)
- etchstop (ES)
- indium-gallium-zinc oxide (IGZO)
- self-aligned
- thin-film transistor (TFT)
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