Abstract
A simulation approach to test generation is developed. Advantages of this approach are that backtracking is completely avoided and circuit delays are taken into account. The method is based on a directed search in the vector space. In order to compute the cost function that is minimized during the search a new form of logic simulation, called the threshold-value simulation, is developed. Logic gates are modeled as threshold functions with the standard definition of threshold functions modified to propagate signal controllability information. The method allows accurate three-value (0, 1, X) simulation of logic circuits and the controllability information is used for test generation and fault simulation. Thus, the threshold-value model provides an unified framework for verification and test.
| Original language | English |
|---|---|
| Title of host publication | Testing and Diagnosis of VLSI and ULSI |
| Publisher | Springer |
| Pages | 311-323 |
| ISBN (Print) | 9789024737949, 9789401071345, 9789400914179 |
| DOIs | |
| Publication status | Published - 1988 |
| Externally published | Yes |