Timing-driven partial scan

A partial scan approach that aims to reduce both area overhead and performance degradation caused by test logic is presented. Given a target speed and an initial design that meets the target, the algorithm selects a minimum set of scan flip-flops, if they exist, that (1) will break all sequential cycles and (2) will not violate the performance requirement after the scan logic is added. If such a set does not exist, the algorithm will find a set of scan flip-flops in which (1) all sequential cycles are broken and (2) the total area increase caused by the scan logic and the subsequent performance optimization is minimized. For circuits synthesized by automatic synthesis tools, the authors suggest a novel design flow, which selects/inserts the partial scan logic after area optimization, but before performance optimization. For meeting both performance and testability requirements, this design flow produces designs with less area increase than the traditional design flow, which considers testability and adds test logic after performance optimization. Experimental results on the ISCAS'89 sequential circuits are presented as well as comparisons between the proposed method and previous methods.