Abstract
Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).
| Original language | English |
|---|---|
| Title of host publication | Phase-Locked Frequency Generation and Clocking |
| Publisher | Institution of Engineering and Technology |
| Pages | 347-378 |
| Number of pages | 32 |
| ISBN (Electronic) | 9781785618857 |
| Publication status | Published - 1 Jan 2020 |
| Externally published | Yes |
Bibliographical note
Publisher Copyright:© The Institution of Engineering and Technology 2020.
Keywords
- Cmos digital integrated circuits
- Digital phase locked loops
- Field effect mimic
- Phase noise
- Power consumption
- Radio transceivers