Abstract
Recent advancements in neural rendering technologies and their supporting devices have paved the way for immersive 3D experiences, significantly transforming human interaction with intelligent devices across diverse applications. However, achieving the desired real-time rendering speeds for immersive interactions is still hindered by (1) the lack of a universal algorithmic solution for different application scenarios and (2) the dedication of existing devices or accelerators to merely specific rendering pipelines. To overcome this challenge, we have developed a unified neural rendering accelerator that caters to a wide array of typical neural rendering pipelines, enabling real-time and on-device rendering across different applications while maintaining both efficiency and compatibility. Our accelerator design is based on the insight that, although neural rendering pipelines vary and their algorithm designs are continually evolving, they typically share common operators, predominantly executing similar workloads. Building on this insight, we propose a reconfigurable hardware architecture that can dynamically adjust dataflow to align with specific rendering metric requirements for diverse applications, effectively supporting both typical and the latest hybrid rendering pipelines. Benchmarking experiments and ablation studies on both synthetic and real-world scenes demonstrate the effectiveness of the proposed accelerator. It achieves real-time rendering speeds (> 30 FPS) and up to 119 × speedups over state-of-the-art neural rendering hardware across varied rendering pipelines, while adhering to power consumption constraints of around 5 W, typical for edge devices. Consequently, the proposed unified accelerator stands out as the first solution capable of achieving real-time neural rendering across varied representative pipelines on edge devices, potentially paving the way for the next generation of neural graphics applications.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2025 IEEE International Symposium on High Performance Computer Architecture, HPCA 2025 |
| Publisher | IEEE Computer Society |
| Pages | 246-260 |
| Number of pages | 15 |
| ISBN (Electronic) | 9798331506476 |
| ISBN (Print) | 9798331506483 |
| DOIs | |
| Publication status | Published - 8 Apr 2025 |
| Externally published | Yes |
| Event | 31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025 - Las Vegas, United States Duration: 1 Mar 2025 → 5 Mar 2025 |
Publication series
| Name | Proceedings - International Symposium on High-Performance Computer Architecture |
|---|---|
| ISSN (Print) | 1530-0897 |
Conference
| Conference | 31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025 |
|---|---|
| Country/Territory | United States |
| City | Las Vegas |
| Period | 1/03/25 → 5/03/25 |
Bibliographical note
Publisher Copyright:© 2025 IEEE.
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