Vector generation for maximum instantaneous current through supply lines for CMOS circuits

Angela Krstic*, Kwang Ting Cheng

*Corresponding author for this work

Research output: Contribution to journalConference article published in journalpeer-review

62 Citations (Scopus)

Abstract

We present two new algorithms for generating a small set of patterns for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. The first algorithm is based on timed ATPG, while the second is a probability-based approach. Both algorithms can handle circuits with arbitrary but known delays and they produce a set of 2-vector tests. Experimental results demonstrating that the outcome of applying our algorithms is a small set of patterns producing a current that is a tight lower bound on the maximum instantaneous current are included.

Original languageEnglish
Pages (from-to)383-388
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA
Duration: 9 Jun 199713 Jun 1997

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