Abstract
We present two new algorithms for generating a small set of patterns for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. The first algorithm is based on timed ATPG, while the second is a probability-based approach. Both algorithms can handle circuits with arbitrary but known delays and they produce a set of 2-vector tests. Experimental results demonstrating that the outcome of applying our algorithms is a small set of patterns producing a current that is a tight lower bound on the maximum instantaneous current are included.
| Original language | English |
|---|---|
| Pages (from-to) | 383-388 |
| Number of pages | 6 |
| Journal | Proceedings - Design Automation Conference |
| DOIs | |
| Publication status | Published - 1997 |
| Externally published | Yes |
| Event | Proceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA Duration: 9 Jun 1997 → 13 Jun 1997 |