Wire sweep study for SOT package array matrix molding with simulation and experimental analysis

Small Outline Transistor (SOT) packages, widely used in consumer electronics, are very small, inexpensive surface-mount plastic molded packages. In order to maximize product throughput, the molded array matrix is employed for products fabrication, which leads to a potential critical wire sweep issue for SOT package during the transfer molding process. The unreasonably large wire sweep will extremely influence the package reliability, and even lead to failure of the product. In this study, both experimental and simulated works were resorted to analyze the wire sweep of SOT package array matrix mold. At the beginning, two different simulation methods, 3D analysis and Dual Domain analysis, were employed to predict the flow pattern and wire sweep during the transfer molding process with a hybrid finite-element/finite-difference method using commercial software Autodesk Moldflow Insight (AMI). It is found that both of the methods can obtain a well matched flow pattern but Dual Domain analysis acquire the more reasonable wire sweep distribution, compared with the experimental observation. Therefore, it can be concluded that the Dual Domain analysis is the more reasonable and recommended method to cope with wire sweep problem. Furthermore, according to the Dual Domain analysis result, it is also found that the sharply increased velocity is the key reason for the wire sweep issue in the vent side of the mold, due to the flow front concentration. In order to address the issue, the transfer mold process optimization with transfer profile was carried out. The simulation results reveal the transfer molding process optimization is an effective way to deal with this problem.