TY - GEN
T1 - Wireless power link design using silicon-embedded inductors for brain-machine interface
AU - Wu, Rongxiang
AU - Raju, Salahuddin
AU - Chan, Mansun
AU - Sin, Johnny K.O.
AU - Yue, C. Patrick
PY - 2012
Y1 - 2012
N2 - This paper discusses the safety requirements, equivalent circuit model, and design strategy of wireless power transmission to neural implants. The most daunting challenge is the design of the integrated receiving coil on the implantable device whose size must be within the safety and regulation limits while providing sufficient power transfer and efficiency. A novel silicon substrate-embedded 3.6-H spiral inductor has been designed to fit inside a 4.5 mm 4.5 mm implantable IC as the receiving coil. Full-wave EM simulations show that in a practical brain-machine interface setting, wireless power in the range of 1-10 mW can be delivered at 5% efficiency to an implant at 1 cm below the head surface using signals between 2 to 5 MHz. To achieve a high transfer efficiency, the optimal impedance for loading the receiving coil is derived using the equivalent circuit parameters of a realistic 3D model of the entire wireless power link. The large parasitic capacitance of the in-chip inductor is methodically absorbed in the matching network to maximize the efficiency and power transfer.
AB - This paper discusses the safety requirements, equivalent circuit model, and design strategy of wireless power transmission to neural implants. The most daunting challenge is the design of the integrated receiving coil on the implantable device whose size must be within the safety and regulation limits while providing sufficient power transfer and efficiency. A novel silicon substrate-embedded 3.6-H spiral inductor has been designed to fit inside a 4.5 mm 4.5 mm implantable IC as the receiving coil. Full-wave EM simulations show that in a practical brain-machine interface setting, wireless power in the range of 1-10 mW can be delivered at 5% efficiency to an implant at 1 cm below the head surface using signals between 2 to 5 MHz. To achieve a high transfer efficiency, the optimal impedance for loading the receiving coil is derived using the equivalent circuit parameters of a realistic 3D model of the entire wireless power link. The large parasitic capacitance of the in-chip inductor is methodically absorbed in the matching network to maximize the efficiency and power transfer.
UR - https://openalex.org/W2127528479
UR - https://www.scopus.com/pages/publications/84864059883
U2 - 10.1109/VLSI-DAT.2012.6212648
DO - 10.1109/VLSI-DAT.2012.6212648
M3 - Conference Paper published in a book
SN - 9781457720819
T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
T2 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Y2 - 23 April 2012 through 25 April 2012
ER -