Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability

A novel six-transistor static random-access memory (6T SRAM) cell is proposed in this paper for enhancing the data stability and write ability as compared to the conventional memory circuits. Asymmetrically gate overlapped/underlapped FinFETs are employed as bitline access transistors in the proposed SRAM cell. The strength of the asymmetrical bitline access transistors are weakened during read operations. Furthermore, voltage transfer characteristics (VTCs) of cross-coupled inverters have narrower transition regions in the new SRAM cell as compared to the conventional SRAM cells. The proposed SRAM cell thereby provides stronger read data stability as compared to the conventional symmetrical SRAM cells. The strength of bitline access transistors are enhanced during write operations as the direction of current flow is reversed in the new asymmetrical SRAM cell. The power supply voltage of a selected word floats during write operations. The write voltage margin is thereby significantly increased with the proposed SRAM cell as compared to the conventional SRAM cells. The read data stability and write ability are both enhanced by up to 51.7% and 65.5%, respectively, with the proposed SRAM cell as compared to the conventional symmetrical six-FinFET SRAM cells in a 15nm FinFET technology.