A DC-48 GHz CMOS all-digital frequency synthesizer for software-defined radios

Abstract

Recently, various communication standards with different carrier frequencies, channel bandwidth, and modulation schemes are widely used every day. The demanding of anywhere and anytime connectivity keeps motivating the industry and academy to find a low cost and low power solution to integrate these different radio access technologies into a portable device with small form factor. Thanks to the continuous scaling down of the CMOS process, which boosts the transistor’s unity gain frequency (f_t) to hundreds of GHz, it has been widely used as a low-cost solution for the integration of wireless transceiver systems from radio frequency (RF) frequency to millimeter-wave (mm-Wave) frequency due to its high integration level and high yield. However, the realization of software-defined radios (SDRs) to perform spectrum reception and transmission across multiple decades of frequencies (e.g. from DC to 60GHz) with highly reconfigurable hardware platform in the CMOS process is still of great challenges. In this thesis, a SDR all-digital frequency synthesizer with novel circuit techniques is proposed in low-cost CMOS process to generate the LO signals from 375 MHz to 48 GHz continuously for the first time. In the all-digital phase-locked loop (ADPLL) for RF frequency synthesis, firstly, the switched-transformer technique is proposed to implement a triple-band quadrature digitally-controlled oscillator (Q-DCO) in 65-nm CMOS process with an ultra-wide frequency tuning range from 6 to 12 GHz. Secondly, a hybrid phase and time to digital converter (PTDC) is proposed to improve both the time resolution and linearity by using the multi-phase signals divided from the wide-band 6 to 12 GHz Q-DCO. For millimeter wave (mm-Wave) frequency synthesis, firstly, a multi-mode magnetically-tuned voltage-controlled oscillator (MT-VCO) using a switched-triple-shielded transformer is proposed to increase the frequency tuning range by changing the magnetic coupling coefficient. Fabricated in 65-nm CMOS process, the MT-VCO measures a continuous tuning range of 44.2% from 57.5 to 90.1 GHz and figure-of-merit with tuning range (FOM_T) between -184.2 and -192.2 dBc/Hz. Secondly, the self-frequency-tracking (SFT) technique is proposed to enhance the locking range of injection-locked frequency dividers (ILFDs) without extra power and area penalties. Fabricated in 65-nm CMOS process, the SFT-ILFD prototype achieves an input locking range of 29% from 53.7 to 72.0 GHz and figure-of-merit (FOM) of 9.53. Finally, the 6 to 12 GHz IQ LO signals generated from the ADPLL is injected into a wideband ×4 injection-locked frequency multiplier (ILFM) with the similar magnetically tuning technique used in the MT-VCO to generate the differential LO signals from 24 to 48 GHz. Followed by two wideband SFT-ILFDs, the12 to 24 GHz IQ LO signals are further obtained. The calibration loop is also proposed to align the free running frequency of the ILFM with 4 times of the injection frequency. From the measurement results, an SDR frequency synthesizer prototype that can generates IQ LO signals from 305 MHz to 23.25 GHz and differential LO signals from 23.25 to 46.5 GHz with sufficiently good phase noise is successfully demonstrated in 65-nm CMOS process.

Date of Award	2013
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology