A digital-to-time converter design for quantization noise compensation in fractional-N phase-locked loops

Abstract

This thesis introduces an arithmetic-based digital-to-time converter (DTC) adopted in fractional-N phase-locked loop (PLL) for quantization noise compensation. This calibration-free DTC eliminates the time-to-phase normalization for quantization noise and the inherent RC nonlinearity in charging and discharging. It processes two periodical inputs: the 10-GHz clock from digital-controlled oscillator (DCO) as the arithmetical time interval and the 80-MHz reference clock from a crystal oscillator (REF) as the DTC operation cycle. The 7-bit DTC prototype, designed in 65-nm CMOS technology, demonstrates a maximum INL and DNL of 0.37% and 0.23% at 600 ps full-scale delay while consuming a power of 1.02 mW and occupying 0.0124 mm² area.

Date of Award	2023
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Jiang XU (Supervisor) & Zhirui ZONG (Supervisor)