A millimeter-wave mixer-first sub-sampling 8-path CMOS receiver with on-chip antenna and LO generator

Abstract

To avoid over-congested RF bands and increase the data rate, wireless communication at millimeter wave has become the main focus for the current 5G and future 6G standard. Beamforming techniques are usually employed for mm-wave wireless communication to compensate for the increased free-space path loss and enable spatial multiplexing. Among different beamforming architectures, the digital beamforming scheme is the most promising one as it can support multiple beams from multiple users simultaneously, which is essential for massive multiple-input-multiple-out systems. Since the entire receiver has to be replicated for each antenna element and the receiver does not benefit from spatial filtering in digital beamforming, a low-power, low-cost receiver with good blocker tolerance and high linearity is in demand. This dissertation is dedicated to a monolithic solution for the target receiver in CMOS technology with innovations at both architecture and circuit levels. While the mixer-first NPF-based receiver fits the target receiver perfectly, its operating frequency is usually limited below 6GHz. To extend its operating frequency to mm-wave, a sub-sampling gapped NPF with a passive recombination scheme is proposed, which substantially relaxes the rise and fall time requirement and hence the power consumption of the LO generator. Therefore, a 10.8GHz to 14.5GHz 8-phase 12.5% duty-cycle LO generator has been fully integrated with a power consumption of 58.3 to 77.8mW. To further increase the integration level and reduce the cost of the complete receiver chain, a dipole antenna with a crossed pattern of artificial magnetic conductors is also integrated on-chip. A six-port transformer-based quadrature hybrid coupler is further proposed to filter out the closest intrinsic harmonic image of the sub-sampling N-path filter in the phase domain and provide load-insensitive impedance matching to the dipole antenna. Finally, the proposed receiver system with the on-chip antenna was fabricated in the TSMC 28nm. Within the frequency range from 48 to 56GHz, the receiver without on-chip antenna measures a peak gain of 17.3dB, a peak input 1dB compression point (IP1dB) of -12dBm, a peak in-band the 3^rd order intercept point at input (IIP3) of 4dBm and a minimum noise figure (NF) of 14.7dB while consuming 83.3 to 102.8mW. For the receiver system with the on-chip antenna, a peak gain of 11dB is measured. At a 25cm air distance, it can achieve a data rate from 0.6 Gbps to 3.6Gbps with an error vector magnitude (EVM) of -27.5 to -24.5dB for 64 quadrature amplitude modulation (QAM) given a smaller than 10^-3 bit error rate requirement.

Date of Award	2023
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Howard Cam LUONG (Supervisor)