Compact modeling of double-gate metal-oxide-semiconductor field-effect transistor

Abstract

Metal-oxide-semiconductor (MOS) field-effect transistor (FET) scaling is a key factor that enabled the IC industry to follow the projection of Moore's law for the past ~35 years. However, this scaling process becomes increasingly difficult as sev-eral limits from both process and device performance are approaching, as the tech-nology node goes to 65nm and beyond. To extend the life of MOSFET scaling, non-classical MOSFETs were introduced to the roadrnap. The double-gate (DG) MOS-FET is one of the most promising candidates. This thesis focuses on modeling of DG MOSFET and covers mainly three parts: general Poisson-Boltzmann solutions, threshold voltage (V_T) modeling of DG MOS capacitor and current-voltage (IV) modeling of DG MOSFET.

Three general classes of solutions are derived, based on three boundary condi-tions, for the governing Poisson-Boltzmann equation of an arbitrary DG MOS ca-pacitor with arbitrary bias conditions. The "zero-field" (F0) and the "zero-potential" (P0) solution regimes are separated by the "zero-field and zero-potential" (PF0) solu-tion. Implications of the general solutions were discussed. Saturation body potential and body electric field were predicted and the equivalence of silicon-on-insulator (SOI) MOS capacitor to a DG counterpart was demonstrated.

Based on the F0 solution, an approximate expression is proposed to explicitly relate the potential and the electric field on the silicon side of the ox-ide/ semiconductor interface of a symmetrical DG MOS capacitor. The resulting ex-pression does not contain the floating-body potential as an implicit variable and is continuously valid fiom the sub-threshold to the quasi-linear operating regime. It is the basis on which the V_T and the IV models of a symmetrical DG MOSFET are de-veloped.

A linearly extrapolated threshold voltage V_Te is analytically derived based on a physically vigorous criterion for the pinning of surface potential. It is predicted, and verified using numerical simulation, that V_Te for a DG MOS capacitor with doped silicon body first decreases and then increases with increasing gate oxide thickness. The gate oxide thickness at the minimum value of V_Te increases with the decreasing doping concentration. It is found that a single expression of V_Te is applicable from fully-depleted DG MOS devices to its bulk counterpart.

A combination of the Pao-Sah integral approach and the gradual-channel ap-proximation (GCA) has been used to derive the IV model of DG MOSFET with in-trinsic silicon body using the proposed electric field-potential relationship and incor-porating also the mobility degradation effect at high vertical electric field and the ve-locity saturation effect at high lateral electric field. The proposed IV model is con-tinuously valid fiom the sub-threshold to the quasi-linear regimes of operation and up to a well defined drain saturation voltage. The length of the velocity saturation region near the drain end, where the GCA does not hold, is obtained by solving a two-dimensional Poisson's equation.

Date of Award	2006
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology