Efficient coding and decoding for wireless and on-chip communications

Abstract

As the use of smart devices continues to grow globally, coupled with advancements in AI technologies, there is a rising interest in 6G communication systems from both the industry and academia. The dawn of the 6G era brings with it the demand for higher data rates and increased reliability. To provide users with superior service quality in complex environments, 6G systems are incorporating AI technologies. However, the power consumption of AI chips used in dense 6G networks is expected to be significant. Out of this concern, the need for low-power AI chips is highlighted. This thesis aims to address diverse requirements of 6G systems and AI chips, viewing them through the lens of coding theory.

First, for achieving high data rates and reliability, the LDLCs with capacity-approaching property are considered. The M-Gaussian decoder is the state-of-the-art message passing decoder for LDLCs in terms of the error performance. However, this decoder has complexity O(M^d−1) with messages represented by Gaussian mixtures, where d is the degree of an LDLC and M is the number of Gaussian functions for approximating each check node message. We establish the correspondence between Gaussian functions for approximating a variable node message and points of a certain lattice. Based on this lattice viewpoint, the problem of approximating a variable node message is formulated as an LPE problem. Then, an LPE decoder with linear complexity O(d) is proposed. Our simulation results validate that the LPE decoder achieves almost the same error performance as the M-Gaussian decoder. As an extension, the LPE decoder is adapted for D-LDLCs which are designed for the applications to relay networks. After characterizing the asymptotic behavior of the message variances, the decoding complexity is shown to be O(d₁ + d₂) where d₁ + d₂ is the degree of a D-LDLC.

Second, we consider the bus code design for reducing the coupling energy dissipation for on-chip communications, which is caused by charging and discharging the coupling capacitance between adjacent bus wires. The code design also necessitates an efficient codec implementation to ensure that the energy savings on buses are not greatly o↵set. As a generalization of the well-known BI codes, the BSDSI codes are proposed for which the indices of message bits to invert vary with di↵erent current bus states and are indicated by binary selection vectors. We first formulate the selection vector design problem for our proposed codes. Then, by leveraging the weight enumerator method, the optimal selection vector design is proved to possess a recursion structure allowing an efficient hardware implementation. The propagation delay of determining optimal selection vectors is of O(k), where k is the message length. Further, we propose a parallel-window design for the selection vectors to reduce the propagation delay from O(k) to O(1). Compared with the uncoded case, the optimal BSDSI code achieves a 32.4% and 26.8% coupling energy saving for k = 4 and 8, respectively, which outperforms the state-of-the-art BI-based code by 9.5% and 4.0% for k = 4 and 8, respectively. Taking the 28-nm codec energy into consideration, the optimal BSDSI code improves over the state-of-the-art code by 5.9% and 2.2% in terms of the overall energy savings for k = 4 and 8, respectively.

Finally, the MBSDSI codes are proposed for further boosting the coupling energy savings. Compared to the BSDSI codes, the selection vectors utilized by the MBSDSI codes depend not only on the current bus states but also on the messages. Serving as the foundation for the selection vector design, several lemmas are proved first using the weight enumerator method. Then, size-4 and size-5 sliding-window designs are proposed with recursion structures that have the propagation delay of O(k) for determining selection vectors. For reducing the propagation delay, the parallel-window design for selection vectors is also demonstrated, leading to the propagation delay of O(1). Compared with the uncoded case, the MBSDSI code with the size-5 sliding-window design achieves a 36.8% and 28.8% coupling energy saving for k = 4 and 8, respectively, which outperforms the optimal BSDSI code by 4.4% and 2.0% for k = 4 and 8, respectively. Taking the 28-nm codec energy into consideration, the MBSDSI code with the size-4 sliding-window design improves over the optimal BSDSI code by 2.8% and 1.1% in terms of the overall energy savings for k = 4 and 8, respectively.

Date of Award	2024
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Wai Ho MOW (Supervisor)