GaN-based device technology advancement for power integration

Abstract

Gallium nitride (GaN) electronic devices are gaining much attention and interest owing to their intrinsic superiority compared to silicon-based counterparts. In the power conversion domain, discrete GaN devices have been substantially advanced and commercialized, positioning themselves in ultra-compact fast chargers and being promising for emerging applications that are power-hungry and yet require compact power supply modules, such as drones, robotics, LiDAR, data centers, etc. To promote GaN’s power electronic technology, the integration-wise advancement becomes highly rewarding at this juncture. It would not only further unlock the potential of discrete GaN devices but also open up freedom of design and engineering at the system level.

Toward high-performance power integration, my thesis work focuses on developing device technologies to enhance the functionality, reliability and stability of GaN-based devices for more versatile power devices, more easy-to-drive power devices, and more energy-efficient peripheral circuits.

Firstly, an area-efficient scheme to seamlessly integrate the commercial power p-GaN gate HEMT and Schottky barrier diode is invented. The transistor cell and diode cell are alternately arrayed along the device width and are locally isolated using ion implantations. The built-in SBD provides a low reverse turn-on voltage which is independent of the threshold voltage and gate bias of the transistor. Compared to the two-device solution using a transistor/diode pair, the proposed RC-HEMT can effectively share the common gate-to-drain access region, which contributes to a main portion of R_ON (ON-resistance × total device width) for a high-voltage GaN power transistor. Compared to device scheme with Schottky contacts distributed at the gate-to-drain access region, the SBD fingers in our work are placed at the source side that is away from high electric-field. Thus, the design of the built-in SBD structure does not affect the performance of the HEMT. To further reduce the R_ON of RC-HEMT, the composition of R_ON of RC-HEMT is analyzed by experimental measurements and numerical simulations. The key to efficient utilization of the RC-HEMT chip area is to identify the optimized ratio of the HEMT source and SBD anode, which are not shared by the reverse conduction and forward conduction. Through proper geometry scaling, R_ON of RC-HEMT can be significantly reduced and be closer to that of a single HEMT.

Secondly, a surface reinforcement technology has been developed to enhance the gate reliability of p-GaN gate HEMTs. The surface of p-GaN is reconstructed into a crystalline GaON that will be in direct contact with the Schottky metal by remote oxygen plasma treatment and subsequently annealed at 800 °C. The GaON exhibits a higher thermodynamic stability and a larger bandgap of ~4.1 eV. Thus, reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime. In addition, such surface reconstruction technology could be applied at the access region of device for improving its immunity to long-term hot electron stress under hard switching. By using same forming process (i.e., oxygen plasma treatment and high-temperature annealing), the surface of AlGaN barrier is converted into a crystalline AlGaON. Devices exhibit substantially suppressed dynamic R_ON degradation after hot-electron stress.

Thirdly, we further leveraged the surface reinforcement technology to create a novel SiN_x/GaON staggered gate stack for stabilizing the p-channel GaN transistor. The type II energy band alignment between SiN_x and GaN automatically nullifies the high-density interface traps near GaN’s valance band maximum, whereas the GaON further reduces the active trap states at the SiN_x/GaON interface. The threshold voltage of GaN p-FETs with such a novel gate stack is barely changed within wide ranges of negative and positive voltage bias and temperature, which thereby enables the implementation of stable GaN complementary logic (CL) circuits. The optimized monolithic GaN CL inverters and ring oscillators preserve decent performances and exhibit high stability over long-period operations and across a temperature range from 25 °C to 400 °C. As such, it becomes much more feasible to build energy-efficient GaN-based CL functional blocks for all-GaN power integration. The gate leakage characteristics and gate reliability of GaN p-FETs with the novel gate stack have been studied. At very low gate voltage, the gate current is dominated by surface hopping. When gate voltage becomes more negative, the intrinsic gate current would become dominant and is limited by holes transport in SiN_x in a Poole-Frenkel conduction. Considering this gate leakage mechanism, the maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1 % gate failure rate. These investigations will provide valuable insights for further engineering of the gate structure for improved gate reliability in the future work.

Date of Award	2022
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Kevin Jing CHEN (Supervisor)