Abstract
New circuit architectures with higher integration levels have been seen as a driving force for continued performance gains beyond traditional technology scaling, from facilitating the rapid development of the neuromorphic computing field, driving a huge demand for memory array simulations. However, the existing circuit simulation methods are not optimized for the unique characteristics of memory devices, that is, the characteristics of dynamic time variation and multiple outputs for the same input voltage. The key point is how to select the appropriate network architecture to make such memory modeling better capture its physical characteristics.In this research work, we propose a method for constructing a memory model capable of describing the quasi-static and dynamic behavior of memory devices. This method employs a recurrent Non-linear Auto Regressive with Exogenous inputs (NARX) network and appropriate network corrections to capture the feature of multilevel resistance states and dynamic temporal variations. The validity of the model is extensively verified through numerical simulations and publicly available experimental data. Building upon the established model, a set of statistical modeling techniques is introduced to account for practical variations in memory devices, including device-to-device variation and time-dependent cycle-to-cycle variation. The feasibility of the model is demonstrated, enabling circuit designers to perform circuit-level simulations within a circuit simulator framework, thereby facilitating a more reliable evaluation of circuits.
| Date of Award | 2024 |
|---|---|
| Original language | English |
| Awarding Institution |
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| Supervisor | Man Sun CHAN (Supervisor) |
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