High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

Abstract

With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Consequently, the embedded systems have led to the advent of multi-core System-on-Chip (MPSoC) design and the high performance computer architectures have evolved into Chip Multi-processor (CMP) platforms. A scalable and modular solution to the interconnecting problem becomes critically important. Network-on-chip (NoC) has been proposed as an efficient solution to handle this distinctive challenge by providing efficient and scalable communication infrastructures among the on-chip resources. In this thesis, we have explored the high performance NoC design for MPSoC and CMP structures from the performance modeling in the offline design phase to the routing algorithm and NoC architecture optimization. More specifically, we first deal with the issue of how to estimate an NoC design fast and accurately in the synthesis inner loop. The simulation based evaluation method besides being slow, provides little insight to guide the optimization process of the NoC synthesis loop. Therefore, fast and accurate analytical models for NoC-based multicore performance evaluation are strongly desired to better explore the design space. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations before the system is built or taped-out. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design with different design constraints and objectives. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bi-directional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel. We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with minimal energy overhead. This proposed NoC architecture exploits the self-reconfigurable bidirectional channels to increase the effective bandwidth and uses express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. From the simulation results on both synthetic traffic and real workload traces, significantly performance improvement in terms of latency and throughput can be achieved.

Date of Award	2014
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology