High-speed NRZ/PAM4 wireline receiver system-on-a-chip design

Abstract

Wireline communication featuring wide bandwidth and good channel isolation has been extensively employed in applications such as massive data centers, cloud computing, etc. In wireline links, I/O transceiver works at the highest data rate and determines the communication quality. Benefitting from the advancement of process technology, the highly demanded I/O bandwidth and power efficiency have been improved dramatically over the past decades, and the trend will continue to meet the future larger data traffic boom. While Moore’s Law is coming to an end, the mainstream non-return-to-zero (NRZ) transceivers meet more stringent challenges, and four-level pulse amplitude modulation (PAM4) transceivers become popular for doubled bandwidth efficiency but with new design challenges. In this thesis, three receivers working at ~25 Gb/s or 56 Gb/s are presented to address these issues. The first work is a source-synchronous low-power 1/4-rate PAM4 receiver with an adaptive variable-gain rectifier (AVGR) based decoder in 28-nm CMOS technology. The proposed AVGR based PAM4-to-NRZ decoder performs gain adaptation and amplitude rectification simultaneously for decoding the least significant bit (LSB) of PAM4 input. The linear sense amplifier (SA) in the AVGR is modified from a latch to achieve both high gain and low power. Experimental results demonstrate that the receiver chip can achieve a BER of 10^-11 and a bit efficiency of 1.38 pJ/bit while receiving and decoding a 24-Gb/s 190-mV_pp PAM4 signal. The second work is a power-efficient source-synchronous NRZ receiver employing a 1/4-rate linear sampling phase detector (LSPD) with embedded feed forward equalizer (FFE) and decision feedback equalizer (DFE). The 1/4-rate LSPD is proposed to save power and avoid dithering jitter in a nonlinear bang-bang PD. To relax the timing constraint and improve the jitter performance of the recovered clock, a 1-tap FFE and a 1-tap DFE are applied to both the data path and the edge path to cancel the first and second post-cursors by reusing the linear samples. The receiver IC is fabricated in a 28-nm CMOS process and achieves error-free operation up to 26 Gb/s with a superior bit efficiency of 0.31 pJ/bit while tolerating a 14-dB channel loss at 13 GHz. The third work is a source-synchronous 56-Gb/s 1/4-rate PAM4 receiver based on two previous works. Besides 1-tap FFE and 1-tap DFE, continuous time linear equalizers (CTLE) are also included to improve the equalization ability. As PAM4 signal is more bandwidth sensitive, the highly demanded adaptation algorithm for the CTLE is proposed based on the data pattern selection scheme. Considering the simplicity and jitter performance, a bang-bang PD with data transition selection is proposed. To alleviate the free running frequency shift of the injection locked ring oscillator (ILRO) used in the first two works and not degrade noise performance, a wide bandwidth phase lock loop (PLL) is employed. The simulation results demonstrate that the receiver achieves a bit efficiency of 0.65 pJ/bit while compensating a 9.5-dB channel loss at 14 GHz. Besides the CTLE adaptation used in the third work, an LMS based adaptation method for DFE is also introduced with design details, which are barely reported before. Behavior-level simulation results reveal the accuracy of the proposed equalization adaptation algorithms.

Date of Award	2018
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology