Mixed-Precision In-Memory Computing SRAM Macro based on Charge Sharing

Abstract

In-memory computing (IMC) has emerged as a promising paradigm to overcome the memory bottleneck in conventional von Neumann architectures by performing computation directly within memory arrays. However, achieving high precision, energy efficiency, and scalability simultaneously remains challenging due to limitations in existing analog computing macros and ADC architectures.

This work proposes precision-reconfigurable and energy-efficient IMC architectures through novel charge sharing schemes and a tailored SAR ADC design. First, a recurrent charge sharing SRAM macro utilizing unit-and double-sized capacitors efficiently supports 2, 4, and 8-bit weights, achieving high area and energy efficiency with operation frequencies up to 667 MHz at 1.2 V and an energy efficiency of 62 TOPS/W. Second, a reconfigurable cascaded charge sharing SRAM macro addresses previous limitations in scalability and throughput by using uniformly sized capacitors to enable weighted summation for 2–8 bit operations. It incorporates a virtual dummy bit strategy to eliminate area overhead and a pipelined architecture to enhance through-put by up to 46.2%, achieving excellent linearity and energy efficiency up to 70 TOPS/W. Finally, a novel passive charge sharing SAR ADC is proposed, featuring efficient 𝑉CM regulation, precharge sharing, and configurable resolution, which achieves 16.99 μW power consumption at 10.4 MS/s while reducing DAC area and power by over 80%. Overall, the proposed circuits offer high precision scalability, reconfigurability, and energy efficiency, making it well suited for mixed-precision IMC applications.

Date of Award	2025
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Man Sun CHAN (Supervisor) & Khawar SARFRAZ (Supervisor)