Multi-phase Clock Generator for High-speed Wireline Transceiver Systems

Abstract

The rapid advancements in Artificial Intelligence (AI) have driven a significant surge in demand for high-speed wireline communication systems. This increasing need for higher data rates calls for power-and area-efficient solutions in data transmission. Clocking circuits, which provide timing references to support various functionalities and directly determine the data rate, are a critical component of wireline systems. However, they also account for a substantial portion of the power overhead, consuming approximately one-third of the total system power. To improve the power efficiency of data links, sub-data-rate clocking architectures have gained popularity among designers due to their ability to reduce power consumption and alleviate bandwidth requirements. These architectures necessitate multi-phase clock generation to produce accurate, low-jitter quadrature clocks, meeting stringent requirements for both random jitter (RJ) and deterministic jitter (DJ) in modern wireline systems to ensure high-quality data transmission.

In this thesis, we present the design and implementation of a novel multi-phase clock generator (QCG) operating within the frequency range of 5 to 10 GHz. The proposed architecture integrates a duty cycle correction (DCC) circuit, a digitally controlled delay line (DCDL), and a two-stage open-loop quadrature error corrector (QEC) to effectively minimize phase errors. Additionally, a finite state machine (FSM) is implemented to perform initial calibration, ensuring optimal QCG performance without introducing extra jitter. The prototype chip occupies a compact area of 0.012 mm^². Measurement results demonstrate a phase error of ≤0.8^° and an integrated RMS jitter of 61.1 fs, with a power consumption of 10.2 mW at 10 GHz operation.

In conclusion, the proposed design offers an open-loop alternative for QCG, delivering competitive performance in terms of noise contribution, power efficiency, and phase accuracy. This design meets the stringent requirements of modern wireline transceivers, making it a promising solution for high-speed communication systems.

Date of Award	2025
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Chik Patrick YUE (Supervisor)