On-chip spatial temperature sensor

Abstract

On-chip spatial temperature sensors are used to perform hotspot detection at different locations of high-speed multi-core CPUs. Each spatial sensor is placed at a different location so that the local temperature information can be digitized and fed back to the thermal management unit. Tasks of the CPU can be assigned according to the local thermal budget of each core. The total number of hotspots can be reduced and thermal related faults can be prevented. The total number of high-power consumption sites is directly proportional to the clock speed and the total number and the complexity of the CPU cores. Compact on-chip spatial temperature sensor should be designed so as to minimize the cost of the high performance multi-core CPU. There are two types of on-chip temperature sensing. The first one is for hotspot detection to signal a thermal fault of a particular CPU core, and an area-efficient low-resolution temperature sensor is needed. The other one is for high-resolution temperature sensing, and a more sophisticated temperature transducer and ΣΔ-based readout electronics is needed. There is tradeoff between the area budget and the temperature resolution requirements. To develop a low-cost solution to satisfy the above two criteria simultaneously, a new sensor architecture using multi-stage noise-shaping (MASH) ΣΔ-ADC (sigma-delta analog-to-digital converter) is proposed. The proposed spatial sensor architecture consists of one BJT-type temperature transducer and one readout electronics using 1^st order ΣΔ-ADC. It can be configured as a hotspot detector that is compatible to an existing thermal management solution. A pair of spatial sensors that are located at two different sites could be transformed to a MASH (1-1) 2^nd order ΣΔ-ADC for high resolution temperature sensing. One of the spatial sensors serves as the temperature sensor, while the other spatial sensor serves as the second-stage of the MASH (1-1) 2^nd order ΣΔ-ADC that suppresses the quantization error of the first cascade stage. Using high order ΣΔ-ADC, not only the temperature sensing resolution is improved but also the total number of conversion cycles can be reduced. Both the 1^st order and MASH (1-1) 2^nd order ΣΔ-ADCs have been designed and fabricated using 0.18μm CMOS process. For the spatial sensor working as a 1^st order ΣΔ-ADC, measurement results show that it can achieve ±1.6°C of min-max accuracy and ±3.2°C of ±3σ accuracy after 2-point trimming. For the spatial sensor working as a MASH (1-1) 2^nd order ΣΔ-ADC, measurement results show that it can achieve ±1.4°C of min-max accuracy and ±3.2°C of ±3σ accuracy after 2-point trimming. Furthermore, the readout throughputs of 1.9k Samples/sec and 7.81k Samples/sec are achieved by the 1^st order ΣΔ-ADC mode and the MASH (1-1) 2^nd order ΣΔ-ADC mode respectively. Measurement results show that the proposed solution can fulfill all on-chip temperature sensing requirements and enhance the flexibility of CPU thermal management design.

Date of Award	2017
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology