On the design of energy-efficient incremental delta-sigma ADCs

Abstract

With the advent of ever pervasive electronics, energy consumption is becoming more and more important. Sensor systems with their readout circuits are ubiquitous in these systems. Designing low energy circuits to enable longer battery lifetime or energy harvesting is crucial. The design of analog-to-digital converters (ADCs) for these breed of circuits is extremely challenging, especially when high resolutions are required. This thesis makes two main contributions. In the first part, we examine the energy-efficiency of incremental ADCs (IADCs), by developing a theoretical model based on noise considerations. Minimum bounds of power consumption and energy-efficiency are presented. A case study and design example are presented to see how well real circuits adhere to these bounds. In the second part, we propose a capacitor scaling technique that exploits the uneven weightage of the decimation filter to improve the energy efficiency of the overall ADC. Coupled with a novel 3-step quantization approach, the ADC maximizes the non-overload range and bandwidth, to achieve a higher signal-to-noise ratio (SNR). Measurement results on a 0.18μm prototype chip demonstrate a 16-bit performance within a 2kHz bandwidth leading to a state-of-art Schreier FoM of 181 dB.

Date of Award	2019
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology