Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) based on GaN-on-Si substrates have been intensively developed and commercialized during the past decades. Nowadays, they have been deployed in high-speed/high-efficiency power conversion systems. However, the development of complementary p-channel GaN field-effect-transistors (FETs) is still in its infancy, as the relatively low mobility of holes in p-GaN makes GaN p-FETs less attractive. Although the GaN complementary device technique might not be a competitive candidate for next-generation cutting-edge CMOS circuits, it could play an irreplaceable role in the GaN-based monolithic power integration by offering the most energy-efficient on-chip peripheral circuit solution for the essential driving, control, sensing, and protection of the power device. The wide-bandgap nature of GaN also makes GaN-based electronics suitable to operate in harsh environments. The commercial p-GaN/AlGaN/GaN-on-Si platform, where a p-GaN layer is intentionally deployed for realizing enhancement-mode (E-mode) HEMTs, provides a highly suitable venue for developing p-FETs and complementary logic circuits. In this thesis, <span style="text-decoration: underline;"> E-mode GaN p-FET technology and complementary logic circuits</span> based on the commercially available p-GaN gate power HEMT platform are developed and studied for the prospective all-GaN power integration. Firstly, <span style="text-decoration: underline;"> buried-channel p-FET structure </span> for realizing E-mode operation simultaneously with reasonable ON-current density is developed. Early attempts to implement E-mode p-FETs encountered a dilemma in balancing the threshold voltage (V
TH), the ON-current, and the ON/OFF ratio, as the gate recess formed by dry etching for E-mode and low leakage current would significantly degrade the channel mobility. In this work, a thicker p-GaN layer is retained to serve as the channel while an oxygen plasma treatment is applied after etching. The implanted oxygen would convert the top surface of p-GaN to be free-of-holes and thereby facilitate the depletion of the channel. The conducting channel is buried by the oxidized surface at the ON-state, away from the detrimental dielectric/etched-semiconductor interface. As a result, the buried p-channel GaN MOSFET demonstrates stringent E-mode operation with a reasonable current density and high ON/OFF ratio. With promising E-mode p-FETs available, a <span style="text-decoration: underline;"> monolithic n-p integration</span> technique on this platform would is developed, and integrated single- and multiple-stage GaN CMOS logic gates are demonstrated. The theoretical speed limit of GaN CMOS on this platform has been derived, revealing that with conventional processing technology in 8-inch lines, an intrinsic logic-gate delay of less than 50 ps is available. It is sufficient for GaN-based power electronic applications where the operating frequencies range from 100 kHz to 10 MHz. A comprehensive set of elementary logic gates and multi-stage logic circuits are demonstrated, which manifest the feasibility of including GaN CMOS in power integration. Particularly, the complementary logic inverters exhibit remarkable performances, including stringent rail-to-rail outputs, substantially suppressed static power dissipation at both logic ‘low’ and ‘high’ states, suitable transition threshold voltages, wide noise margins, and good thermal stability. With the feasibility proven, <span style="text-decoration: underline;"> examination and enhancement of the device/circuit stability</span> are essential for future commercialization. The stability of the buried-channel p-FET is characterized and analysed. It is revealed that there could be a parasitic 2DEG channel under the E-mode p-channel which does not induce significant stability issues. However, the interface between Al
2O
3 and p-GaN could cause pronounced V
TH instability. An alternative gate stack structure featuring SiN
x as the dielectric is proposed and characterized. Thanks to the type-II band alignment between SiNx and GaN, excessive holes could be drained out to the gate electrode, and thereby the V
TH shift is partially suppressed. The results suggest that ‘SiN
x/GaN’ gate stack would be more suitable for the buried channel p-FET, whereas further optimization of the interface remains to be the future work.
| Date of Award | 2021 |
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| Original language | English |
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| Awarding Institution | - The Hong Kong University of Science and Technology
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| Supervisor | Kevin Jing CHEN (Supervisor) |
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