Power management for wearable biomedical system-on-chips

Abstract

Power management is very important for a wearable biomedical electronic system. Advanced devices are highly integrated with many integrated circuit (IC) blocks that make up a System-on-Chip (SoC). For wearable biomedical applications, the number of external components such as inductors and capacitors should be minimized to reduce the PCB (printed circuit board) layout space and manufacturing cost. Fully-integrated power management units (PMUs) are preferred. This research focuses on fully-integrated PMU techniques of high performance low-dropout regulators (LDOs) and switched-capacitor (SC) converters for wearable biomedical applications. The first part of this thesis deals with designing clean analog power supply for bio-signal analog frontend (AFE) readout channels. First, an output-capacitor-free adaptively-biased LDO is proposed to achieve optimized tradeoff between power efficiency, area efficiency, transient speed, and power supply rejection (PSR). A novel PSR enhancer is integrated into the reference buffer that enhances the PSR by 30 dB in the bio-signal frequency range (DC to 1 MHz), and maintains high area- and power-efficiency. A current-controlled pole-tracking frequency compensation network is also proposed that maintains sufficient gain margin (GM) and phase margin (PM) over a wide load current range (0 μA to 20 mA). A second LDO with ultra-high PSR is designed for wearable bioelectronics with low supply voltage (0.9 to 1 V). It consists of two cascoding power stages and the total dropout voltage is designed to be 200 mV. The PSR is better than -110 dB over the bio-signal’s bandwidth. These two designs were designed and fabricated in 0.18 μm CMOS process, and measurement results verified the effectiveness of the proposed techniques. The second part of this thesis deals with dynamic voltage and frequency scaling (DVFS) of the power supply for embedded microcontroller unit (MCU) used in a wearable biomedical SoC. First, a new small-signal model is proposed for analyzing SC converters. It describes the converter in the s-domain accurately and reveals the frequency dependency of the nonlinear DC gain. This nonlinear characteristic has posed difficulty in designing a versatile analog controller for SC converters. The precision of the proposed model is verified by a simulated SC converter test-bench circuit. Second, a frequency-dependent proportional-integral (PI) controller is proposed for SC converters. It is designed to compensate for the nonlinear behaviors of the SC converter, and to maintain system stability over a wide output power range (5 μW to 5 mW). Compared with digital hysteresis controllers, the proposed analog controller could improve the system efficiency by removing the high-frequency system clock. The proposed frequency-dependent PI controller was experimentally verified by a prototype fabricated in a standard 0.13 μm CMOS process.

Date of Award	2021
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Wing Hung KI (Supervisor)