Silicon-based transmitter design for optical fiber communications

Abstract

Explosive increase of the data created by cutting-edge information technologies such as artificial intelligence and cloud computing demands intra- and inter-data center interconnects with higher data rate, higher power efficiency and lower latency. Fiber-based optical links outperform copper-based electrical links especially in terms of channel loss and bandwidth, and hence becoming the mainstream choice for communication scenarios with data rate-distance products beyond 100 Gb/s·m. However, imperfections of optical devices such as VCSEL and optical modulators emerge as bottlenecks for further improvements of the link speed and power efficiency. This thesis focuses on the silicon-based transmitter design for resolving those imperfections, to enhance the qualities of short-reach and long-haul optical fiber communications. In the first part, a 56-Gb/s PAM-4 transmitter with piecewise compensation scheme in 40-nm CMOS is proposed to settle the non-idealities of VCSELs including electrical-to-optical (E/O) gain nonlinearity, E/O bandwidth nonlinearity and asymmetric responses to rising/falling transitions. A unary-based architecture with variable Gm-cells, 2-tap feed-forward equalizer (FFE), continuous-time linear equalizer (CTLE) and falling edge pre-emphasis is adopted to separately control the amplitudes, widths, and skews of three optical PAM-4 sub-eyes. Measurements at 56-Gb/s PAM-4 demonstrate that the proposed piecewise compensation scheme enhances the average sub-eye amplitude/width, ratio-of-level mismatch (RLM) and horizontal skew of the optical PAM-4 signal by 14%/12%, 38% and 63%, respectively. Fabricated in 40-nm CMOS, the transmitter achieves a de-embedded OMA of 1.18 mW and delivers an energy efficiency of 2.05 pJ/b at 56-Gb/s PAM-4. In the second part, a 56-Gbaud half-rate linear transmitter in 130-nm SiGe BiCMOS is presented for optical modulators. The transmitter features an analog multiplexer with inherent feed-forward equalizer (AMUX-FFE) and a large-swing linear driver. The AMUX-FFE provides 2-to-1 analog serialization as well as 3-tap re-configurable FFE to boost the bandwidth of the E/O system. The linear driver adopts a dynamic triple-stacked topology where the bases of stacked transistors are dynamically biased according to the input signal, to achieve large output swing while avoiding breakdown issues. Measurements show that the output driver achieves a DC gain of 17 dB, a 3-dB bandwidth of 38 GHz, and a THD of 1.6% at 1-GHz 6-V_ppd sinusoidal output, and the whole transmitter is capable of outputting 56-Gb/s 7.3-V_ppd NRZ and 112-Gb/s 4.2-V_ppd PAM-4 signals. Finally, in the third part, a 100-Gbaud distributed linear driver with built-in 5-tap FFE in 130-nm SiGe BiCMOS is presented to further improve the data rate and equalization capability of optical modulator-based links. A distributed topology with cross-folded transmission line and cross-coupled Gm cells is proposed to simultaneously utilize transmission lines as inductance for parasitics compensation and delay elements for equalization. Measurements confirm that the proposed driver achieves a DC gain of 10 dB, a 3-dB bandwidth of >67 GHz, and a gain peaking of 6.9 dB at 50 GHz with the FFE turned on. The driver can support the generation of 100-Gb/s 4-V_ppd NRZ signal and 160-Gb/s 3.8-V_ppd PAM-4 signal with a RLM of 95.8%.

Date of Award	2025
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Chik Patrick YUE (Supervisor) & Quan Pan (Supervisor)