Solder bumping for flip-chip applications

Abstract

An advanced packaging technology (developed over 40 years ago) which has begun to generate renewed interest is the solder-bumped flip chip technology. This interconnection method offers significant advantages over other traditional packaging technologies of wire- and tape-automated-bonding. Some of the competitive advantages of flip-chip include the capacity to accommodate a much higher pin count (due to area versus perimeter-only bonding), enhanced electrical and thermal performance, a self-alignment capability at a more relaxed I/O pitch which leads to a lower cost and more manufacturable process, compatibility with current surface mount technology (SMT), and the relative ease in the reworking of defective die.

In this thesis we will detail a successful combination of materials and processes which were developed for fabrication of eutectic lead-tin solder bumps. The potential for realizing a low cost solder bumping process using conventional electroplating and reflow techniques in conjunction with a flip chip assembly process will be presented in detail. Initial results with the flip-chip bonding of specially designed "daisy-chain" solder bumped test die together with preliminary electrical and mechanical characterization of the bonded parts will also be discussed.

This research has proven the feasibility and development of a low-cost solder-bumped process for flip-chip applications. We have found that a manufacturing scale implementation of this technology may be possible provided that the materials and process parameters are properly chosen and controlled.

Date of Award	1999
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology