Three-dimensional perovskite nanowires array based memristor devices

Abstract

Memristor devices are promising candidates for next-generation memory and neuromorphic computing systems. Resistive random access memory (RRAM), a typical memristor device, has been shown with nonvolatile and fast dynamic operation features, bridging the gap between the traditional volatile and fast dynamic RAMs and the nonvolatile and slow FLASH memories. By rationally designing the resistive layer and electrode materials, RRAM devices can operate under electrochemical metallization or valence charge mechanisms, offering an effective strategy to optimize the device performance from the perspective of material engineering. Among those, metal halide perovskite (MHP) outstands for its excellent electrical properties, tunable material structures, and flexible preparation methods, making it an incredible choice for RRAM resistive switching layers.

Herein, this work presents an effective approach to optimizing the RRAM device performance by using MHP nanowires array as resistive switching layers. Specifically, the stability of the MHP nanowires is improved via fabrication in porous aluminum thin films. With the Ag-based electrochemical electrode, ultrafast switching speed (200 ps for monocrystalline MAPbI₃) and ultralong retention time (~7 × 10⁹ s extrapolated for polycrystalline MAPbCl₃) are realized in the obtained high-density three-dimensional MHP nanowires array based RRAM. Meanwhile, a trade-off between device switching speed and retention time is found during the study of three types of methyl ammonium lead halide perovskites (MAPbX₃; X = Cl, Br, I) based RRAMs. Thus, ultrafast switching speed and ultralong extrapolated retention time can be obtained by selecting different NWs array based devices.

To empower the perovskite-based memristor with programmable multilevel states for the synaptic activities simulation of neuromorphic computing, polycrystalline MHP nanowires with a vertical-crystal-stack structure are fabricated as the resistive switching layer. The corresponding devices exhibit highly programmable short-term and robust long-term plasticity traits akin to neural synapses, of which the underlying mechanism is also investigated through first principle simulations. The continuous programmable conductance states feature is well demonstrated by applying the devices in a matrix processing unit for the in-image font conversion.

Integrating RRAM on a CMOS driver platform is highly desirable for advanced functionality. To this end, this work explores the on-chip integration of MHP nanowire based RRAM devices with NMOS FETs using a CMOS-compatible process and realizes the on-chip integration of fundamental 1T-1R cells for memory crossbar switches. As a result, the memory cell shows superior robustness, uniformity, and multilevel programmability.

Date of Award	2022
Original language	English
Awarding Institution	The Hong Kong University of Science and Technology
Supervisor	Zhiyong FAN (Supervisor)