Projects per year
Personal profile
Research interests
Electronic & Computer Engineering - Computer architecture
Electronic & Computer Engineering - Very large-scale integration (VLSI)
Electronic & Computer Engineering - Electronic design automation
Electronic & Computer Engineering - Machine learning
Electronic & Computer Engineering - Very large-scale integration (VLSI)
Electronic & Computer Engineering - Electronic design automation
Electronic & Computer Engineering - Machine learning
Position Held
Director of Institute of Integrated Circuits and Systems
Director of HKUST-SDU Intelligent Computing Joint Laboratory
Director of HKUST and Intel Joint Laboratory
Director of HKUST-SDU Intelligent Computing Joint Laboratory
Director of HKUST and Intel Joint Laboratory
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
Related documents
Education/Academic qualification
PhD in Computer Engineering, PhD, Princeton University
2002
Fingerprint
Dive into the research topics where Yuan XIE is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 1 Similar Profiles
Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
Projects
- 5 Active
-
Design Explorations for 3D Integration Architecture using Hybrid Bonding Technologies
XIE, Y. (PI)
1/10/25 → 30/09/28
Project: Research
-
Development of the Fundamental Technologies of Multimodal Ultrasound-Based Large Foundation Models for Fetal Brain Developmental Abnormalities Diagnosis
LIN, J. (CoI), TANG, Z. (CoI), LIAO, Y. (CoI), YANG, W. (CoI), LI, X. (PI), LI, S. (CoI), LI, K. (PI), QIN, Y. (CoI), CHENG, K.-T. T. (CoI) & XIE, Y. (CoI)
1/01/25 → 31/12/28
Project: Research
-
Memory-Centric Architecture Innovations for Emerging Applications
XIE, Y. (PI)
1/09/24 → 31/08/27
Project: Research
-
Joint Laboratory of Microelectronics
LAW, M. Y. (CoI), YEUNG, C. F. (CoI), POON, A. W. O. (CoPI), SHI, B. E. (CoPI), CHEN, K. J. (PI), WONG, M. H. (CoPI), YUE, C. P. (CoPI), SHAO, Q. (CoPI), SHEN, Y. (CoPI), XIE, Z. (CoPI), WONG, A. K. F. (CoI), CHAN, M. S. (CoPI), YAO, S. (CoPI), KWOK, K. C. (CoI), WONG, C. K. (CoI), LEE, P. M. W. (CoI), CHAN, T. S. (CoI), LI, H. (CoI), KWOK, H. C. (CoI), CHEUNG, T. L. (CoI), YIP, P. K. (CoI), MAN, P. K. R. (CoI), ZHAO, S. (CoI), LAO, S. Y. (CoI), LEE, W. T. (CoI), PUN, Y. C. P. (CoI), LEE, R.S.-W. (CoPI), CHENG, K.-T. T. (CoPI) & XIE, Y. (CoPI)
Joint Laboratory Funding Scheme
1/01/24 → 31/12/28
Project: Research
Research output
-
A Tightly Coupled AI-ISP Vision Processor
Zhang, H., Li, S., Gui, Y., Li, Z., Xu, S., Lu, Y., Niu, D., Zheng, H., Chen, Y. K., Xie, Y. & Fan, Y., 2025, In: IEEE Transactions on Circuits and Systems for Video Technology. 35, 5, p. 4506-4520 15 p.Research output: Contribution to journal › Journal Article › peer-review
1 Citation (Scopus) -
DSTC: Dual-Side Sparse Tensor Core for DNNs Acceleration on Modern GPU Architectures
Zhang, C., Wang, Y., Xie, Z., Guo, C., Liu, Y., Leng, J., Ji, Z., Xie, Y. & Huang, R., 2025, In: IEEE Transactions on Computers. 74, 2, p. 341-355 15 p.Research output: Contribution to journal › Journal Article › peer-review
2 Citations (Scopus) -
Enabling Efficient Sparse Multiplications on GPUs With Heuristic Adaptability
Xu, J., Huang, S., Li, J., Huang, G., Xie, Y., Wang, Y. & Dai, G., 2025, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 44, 6, p. 2226-2239 14 p.Research output: Contribution to journal › Journal Article › peer-review
-
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator
Liang, L., Gu, Z., Zhang, F., Chen, Z., Li, Z., Fan, X., Niu, D., Li, M., Li, Z., Wang, Z., Zheng, H., Cai, Y. & Xie, Y., 19 Sept 2025, In: ACM Transactions on Architecture and Code Optimization. 22, 3, 23 p., 114.Research output: Contribution to journal › Journal Article › peer-review
Open Access -
MemTunnel: A CXL-based Rack-Scale Host Memory Pooling Architecture for Cloud Service
Guan, T., Guan, Y., Du, Z., Ma, J., Tian, B., Wang, Z., Ma, T., Liu, Z., Kong, Y., Xie, Y., Gao, M., Sun, G., Zheng, H. & Niu, D., 2025, In: IEEE Transactions on Parallel and Distributed Systems. 36, 11, p. 2182-2197 16 p.Research output: Contribution to journal › Journal Article › peer-review
Awards
-
Distinguished Artifact Evaluation Awards
XIE, Y. (Recipient), Apr 2024
Prize: Best Paper Award and Prize
-
ZGC Forum Top-100 New Technologies and Products
TU, F. (Recipient) & XIE, Y. (Recipient), May 2023
Prize: Honorary Award